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Contents

  1. Preface
  2. Chapter 1 Understanding an Overview of Domain Configuration
    1. Click 1.1 SPARC M12/M10 Domain Configurations
    2.  1.2 SPARC M12/M10 Hardware Resources
    3. Click 1.3 What is a Physical Partition?
    4. Click 1.4 What is a Logical Domain?
    5. Click 1.5 What is Physical Partition Dynamic Reconfiguration?
    6. Click 1.6 Mixed Use of the SPARC64 X+ Processor and SPARC64 X Processor
  3. Chapter 2 Conditions and Settings for System Operation
    1. Click 2.1 XSCF Status Management
    2. Click 2.2 XSCF Conditions and Settings
    3. Click 2.3 Oracle Solaris Conditions and Settings
    4. Click 2.4 Logical Domain Conditions and Settings
    5. Click 2.5 Dynamic Reconfiguration Conditions and Settings
    6. Click 2.6 Considerations When Using the SPARC64 X+ Processor
  4. Chapter 3 Operations for Domain Configuration
    1. Click 3.1 Operations and Commands Related to Physical Partition Configurations
    2. Click 3.2 Operations and Commands Related to Logical Domain Configurations
  5. Chapter 4 Configuring a Physical Partition
    1.  4.1 Physical Partition Configuration Flow
    2.  4.2 Configuring and Operating a Physical Partition
  6. Chapter 5 Logical Domain Configuration Example
    1.  5.1 Logical Domain Configuration Flow
    2. Click 5.2 Example of Logical Domain Configuration Operations
  7. Chapter 6 Physical Partition Reconfiguration
    1. Click 6.1 Flow for Physical Partition Reconfiguration
    2. Click 6.2 Example of System Board Addition
    3. Click 6.3 Example of Operations for Deleting a System Board
    4.  6.4 Example of Operations for Moving a System Board
    5.  6.5 Example of Operations for Replacing a System Board
    6.  6.6 Considerations When Changing a Physical Partition Number
  8. Chapter 7 Migrating a Guest Domain
    1. Click 7.1 Overview
    2.  7.2 Migrating a Guest Domain
    3.  7.3 Guest Domain Migration Example
  9. Appendix A Environment Configuration Examples and Procedures Using Physical Partition Dynamic Reconfiguration
    1. Click A.1 Updating a System That Does Not Support Physical Partition Dynamic Reconfiguration to One That Does Support It
    2. Click A.2 For New Installations from XCP 2220 or Later, Where the Logical Domain Configuration Has No Free Space for Hardware Resources
    3. Click A.3 For New Installations from XCP 2220 or Later, Where the Logical Domain Configuration Has Free Hardware Resources
    4. Click A.4 For Expansion of a Newly Installed System of Version XCP 2220 or Later from the 1BB to 2BB Configuration
    5. Click A.5 For Installation of the System Board Configured by the SPARC64 X+ Processor to the Physical Partition Configured Only by the SPARC64 X Processor
    6. Click A.6 For Active Replacement of a System Board in a Configuration with Only the Control Domain (for Oracle VM Server for SPARC 3.2 or Later)
  10. Appendix B Supplementary Information for Using Dynamic Reconfiguration
    1. Click B.1 Considerations for the XSCF Reboot or Failover Time
    2.  B.2 Supplementary Information on CPU Operational Mode
    3.  B.3 Other Considerations
  11. Appendix C Meanings of Messages and Corresponding Corrective Action
    1. Click C.1 Command Messages

1.2 SPARC M12/M10 Hardware Resources


1.2 SPARC M12/M10 Hardware Resources
This section describes the hardware resources of the SPARC M12/M10 system.
The SPARC M12/M10 system allows hardware resources, such as CPUs, memory, and I/Os, to be assigned flexibly, enabling efficient use of the resources.
Figure 1-13 shows an example of efficient use of the SPARC M12-1/M10-1 hardware resources.
Figure 1-13  Efficient Use of Hardware Resources (SPARC M12-1/M10-1)
Figure 1-13 Efficient Use of Hardware Resources (SPARC M12-1/M10-1)<span class= "/>
Figure 1-14 shows an example of efficient use of the hardware resources of SPARC M12-2/M12-2S/M10-4/M10-4S.
Figure 1-14  Efficient Use of Hardware Resources (SPARC M12-2/M12-2S/M10-4/M10-4S)
Figure 1-14 Efficient Use of Hardware Resources (SPARC M12-2/M12-2S/M10-4/M10-4S)<span class= "/>
  1. CPU resources
    [SPARC M12-1]
    The resources made available by CPU Activation are a maximum of 6 CPU cores.

    [SPARC M12-2/M12-2S]
    The resources made available by CPU Activation are a maximum of 24 CPU cores (in a 2-CPU configuration).

    [SPARC M10-1]
    The resources made available by CPU Activation are a maximum of 16 CPU cores.

    [SPARC M10-4/M10-4S]
    The resources made available by CPU Activation are a maximum of 32 CPU cores (in a 4-CPU configuration).
  1. Memory resources
    Memory mirroring can be configured for all models. In that case, the amount of available memory is halved.
    [SPARC M12-1]
    Up to 1 TB can be mounted.

    [SPARC M12-2/M12-2S]
    Up to 2 TB can be mounted (in a 2-CPU configuration).

    [SPARC M10-1]
    Up to 1 TB can be mounted.

    [SPARC M10-4/M10-4S]
    Up to 4 TB can be mounted (in a 4-CPU configuration).
  1. I/O resources
    [SPARC M12-1]
    Up to three PCIe cards can be mounted. By connecting a PCI expansion unit, up to 33 PCIe cards can be mounted. Up to eight internal storage units can be mounted.

    [SPARC M12-2/M10-4]
    The SPARC M12-2/M10-4 allows up to 11 PCIe cards to be mounted. By connecting a PCI expansion unit, up to 71 PCIe cards can be mounted. Up to eight internal storage units can be mounted.

    The number of PCIe cards can be increased dynamically using the PHP.

    [SPARC M12-2S/M10-4S]
    The SPARC M12-2S/M10-4S allows up to eight PCIe cards to be mounted. By connecting a PCI expansion unit, up to 58 PCIe cards can be mounted. Up to eight internal storage units can be mounted.

    The number of PCIe cards can be increased dynamically using the PHP.

    [SPARC M10-1]
    The SPARC M10-1 allows up to three PCIe cards to be mounted. By connecting a PCI expansion unit, up to 23 PCIe cards can be mounted. Up to eight internal storage units can be mounted.
  1. Building block configuration (SPARC M12-2S/M10-4S)
    A system with a building block configuration that consists of multiple SPARC M12-2S/M10-4S units can be expanded gradually from 1 block to up to 16 blocks by stacking blocks, with a chassis used as a block.
Figure 1-15  Efficient Use of Hardware Resources in a Building Block Configuration
Figure 1-15 Efficient Use of Hardware Resources in a Building Block Configuration
  1. CPU Activation
    The CPU Activation function can be used to add CPU resources at the granularity of CPU cores, which are a smaller unit than CPU chips.
    You can start with the minimum required CPU resources and gradually expand the CPU resources by adding CPU Activations.
    For details on CPU Activation, see "Chapter 5 CPU Activation" in the Fujitsu SPARC M12 and Fujitsu M10/SPARC M10 System Operation and Administration Guide.
Figure 1-16  CPU Activation (Example of SPARC M10-4/M10-4S)
Figure 1-16 CPU Activation (Example of SPARC M10-4/M10-4S)

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